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author | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2013-12-05 15:51:35 +0200 |
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committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2013-12-17 13:17:54 +0100 |
commit | 6c8b6c288783b05733de31fb61fc8ebfa8ae0229 (patch) | |
tree | 52302ef3d166ce9f71c2fa20525b0c9b573f20be /drivers/gpu/drm/i915/intel_pm.c | |
parent | 0ba22e26fe47b2a216e5438292aeeb8e015e9d64 (diff) | |
download | lwn-6c8b6c288783b05733de31fb61fc8ebfa8ae0229.tar.gz lwn-6c8b6c288783b05733de31fb61fc8ebfa8ae0229.zip |
drm/i915: Disable FBC WM on ILK, and disable LP2+ when FBC is enabled
ILK has a bunch of issues with FBC. First of all, BSpec tells us that
FBC WM should never be enabled. Secondly when FBC is enabled
with FBC WM disabled, LP2+ watermarks must be disabled.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_pm.c')
-rw-r--r-- | drivers/gpu/drm/i915/intel_pm.c | 17 |
1 files changed, 16 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index a65d8816c1e6..3d4daa1fc3be 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -2701,7 +2701,8 @@ static void ilk_wm_merge(struct drm_device *dev, config->num_pipes_active > 1) return; - merged->fbc_wm_enabled = true; + /* ILK: FBC WM must be disabled always */ + merged->fbc_wm_enabled = INTEL_INFO(dev)->gen >= 6; /* merge each WM1+ level */ for (level = 1; level <= max_level; level++) { @@ -2721,6 +2722,20 @@ static void ilk_wm_merge(struct drm_device *dev, wm->fbc_val = 0; } } + + /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */ + /* + * FIXME this is racy. FBC might get enabled later. + * What we should check here is whether FBC can be + * enabled sometime later. + */ + if (IS_GEN5(dev) && !merged->fbc_wm_enabled && intel_fbc_enabled(dev)) { + for (level = 2; level <= max_level; level++) { + struct intel_wm_level *wm = &merged->wm[level]; + + wm->enable = false; + } + } } static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm) |