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| author | Damien Lespiau <damien.lespiau@intel.com> | 2014-11-04 17:07:01 +0000 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2014-11-07 18:42:14 +0100 |
| commit | 34bb56af7fae9d4d6a33bf6f5f915e75a4023e02 (patch) | |
| tree | 9324f6fab1368a16f7cbd23b5ed5c9e51cfbe22e /drivers/gpu/drm/i915/intel_pm.c | |
| parent | 5d374d9638924ff8c91a87f55dc895be7ab163f8 (diff) | |
| download | lwn-34bb56af7fae9d4d6a33bf6f5f915e75a4023e02.tar.gz lwn-34bb56af7fae9d4d6a33bf6f5f915e75a4023e02.zip | |
drm/i915/skl: Stage the pipe DDB allocation
To correctly flush the new DDB allocation we need to know about the pipe
allocation layout inside the DDB in order to sequence the re-allocation
to not cause a newly allocated pipe to fetch from a space that was
previously allocated to another pipe.
This patch preserves the per-pipe (start,end) allocation to be used in
the flush.
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_pm.c')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_pm.c | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 7fdccba93385..cd2b3351ff45 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -3119,13 +3119,13 @@ skl_allocate_pipe_ddb(struct drm_crtc *crtc, struct drm_device *dev = crtc->dev; struct intel_crtc *intel_crtc = to_intel_crtc(crtc); enum pipe pipe = intel_crtc->pipe; - struct skl_ddb_entry alloc; + struct skl_ddb_entry *alloc = &ddb->pipe[pipe]; uint16_t alloc_size, start, cursor_blocks; unsigned int total_data_rate; int plane; - skl_ddb_get_pipe_allocation_limits(dev, crtc, config, params, &alloc); - alloc_size = skl_ddb_entry_size(&alloc); + skl_ddb_get_pipe_allocation_limits(dev, crtc, config, params, alloc); + alloc_size = skl_ddb_entry_size(alloc); if (alloc_size == 0) { memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe])); memset(&ddb->cursor[pipe], 0, sizeof(ddb->cursor[pipe])); @@ -3133,11 +3133,11 @@ skl_allocate_pipe_ddb(struct drm_crtc *crtc, } cursor_blocks = skl_cursor_allocation(config); - ddb->cursor[pipe].start = alloc.end - cursor_blocks; - ddb->cursor[pipe].end = alloc.end; + ddb->cursor[pipe].start = alloc->end - cursor_blocks; + ddb->cursor[pipe].end = alloc->end; alloc_size -= cursor_blocks; - alloc.end -= cursor_blocks; + alloc->end -= cursor_blocks; /* * Each active plane get a portion of the remaining space, in @@ -3147,7 +3147,7 @@ skl_allocate_pipe_ddb(struct drm_crtc *crtc, */ total_data_rate = skl_get_total_relative_data_rate(intel_crtc, params); - start = alloc.start; + start = alloc->start; for (plane = 0; plane < intel_num_planes(intel_crtc); plane++) { const struct intel_plane_wm_parameters *p; unsigned int data_rate; |