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| author | Imre Deak <imre.deak@intel.com> | 2014-03-27 17:45:10 +0200 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2014-04-01 22:58:18 +0200 |
| commit | d60c4473b6f54876cb7e6bdb7fefee8ccb0d626f (patch) | |
| tree | fcc5b97da7ffc2bffc9732c169d8101234b70f1c /drivers/gpu/drm/i915/intel_pm.c | |
| parent | 0d8f94912a2e204a0faeac30f4d29f14aa05ee89 (diff) | |
| download | lwn-d60c4473b6f54876cb7e6bdb7fefee8ccb0d626f.tar.gz lwn-d60c4473b6f54876cb7e6bdb7fefee8ccb0d626f.zip | |
drm/i915: vlv: cache current CD clock rate
Instead of reading out the CD clock rate from the HW at each modeset, do
this only during driver init and resume and use the cached value during
modeset. This moves things towards a state where the sw and hw side
setup is separated. It's also needed for VLV RPM, where we don't put
device into D0 state until modeset_global_resources is called and thus
can't access any display/gfx registers.
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Antti Koskipää <antti.koskipaa@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_pm.c')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_pm.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 9277265dc9a6..fab8ad45a612 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -5078,6 +5078,10 @@ static void valleyview_init_clock_gating(struct drm_device *dev) } DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv->mem_freq); + dev_priv->vlv_cdclk_freq = valleyview_cur_cdclk(dev_priv); + DRM_DEBUG_DRIVER("Current CD clock rate: %d MHz", + dev_priv->vlv_cdclk_freq); + I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE); /* WaDisableEarlyCull:vlv */ |