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authorVille Syrjälä <ville.syrjala@linux.intel.com>2013-07-05 11:57:13 +0300
committerDaniel Vetter <daniel.vetter@ffwll.ch>2013-08-05 19:03:55 +0200
commitbdd57d0386d892e5c470a3d615c3034389700964 (patch)
tree460fff0732f034ab4cb1dc1c7d7da7b1688b1c26 /drivers/gpu/drm/i915/intel_pm.c
parent2c1792a10b10e41dcf34c97304fb8f75e52e7112 (diff)
downloadlwn-bdd57d0386d892e5c470a3d615c3034389700964.tar.gz
lwn-bdd57d0386d892e5c470a3d615c3034389700964.zip
drm/i915: Add scaled paramater to update_sprite_watermarks()
For calculating watermarks we want to know whether sprites are scaled. Pass that information to update_sprite_watermarks() so that eventually we may do some watermark pre-computing. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_pm.c')
-rw-r--r--drivers/gpu/drm/i915/intel_pm.c13
1 files changed, 7 insertions, 6 deletions
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index b503f594205e..f9813b3ead34 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -2403,7 +2403,7 @@ static void hsw_compute_wm_parameters(struct drm_device *dev,
pipe = intel_plane->pipe;
p = &params[pipe];
- p->sprite_enabled = intel_plane->wm.enable;
+ p->sprite_enabled = intel_plane->wm.enabled;
p->spr_bytes_per_pixel = intel_plane->wm.bytes_per_pixel;
p->spr_horiz_pixels = intel_plane->wm.horiz_pixels;
@@ -2631,7 +2631,7 @@ static void haswell_update_wm(struct drm_device *dev)
static void haswell_update_sprite_wm(struct drm_device *dev, int pipe,
uint32_t sprite_width, int pixel_size,
- bool enable)
+ bool enabled, bool scaled)
{
struct drm_plane *plane;
@@ -2639,7 +2639,8 @@ static void haswell_update_sprite_wm(struct drm_device *dev, int pipe,
struct intel_plane *intel_plane = to_intel_plane(plane);
if (intel_plane->pipe == pipe) {
- intel_plane->wm.enable = enable;
+ intel_plane->wm.enabled = enabled;
+ intel_plane->wm.scaled = scaled;
intel_plane->wm.horiz_pixels = sprite_width + 1;
intel_plane->wm.bytes_per_pixel = pixel_size;
break;
@@ -2727,7 +2728,7 @@ sandybridge_compute_sprite_srwm(struct drm_device *dev, int plane,
static void sandybridge_update_sprite_wm(struct drm_device *dev, int pipe,
uint32_t sprite_width, int pixel_size,
- bool enable)
+ bool enable, bool scaled)
{
struct drm_i915_private *dev_priv = dev->dev_private;
int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */
@@ -2850,13 +2851,13 @@ void intel_update_watermarks(struct drm_device *dev)
void intel_update_sprite_watermarks(struct drm_device *dev, int pipe,
uint32_t sprite_width, int pixel_size,
- bool enable)
+ bool enable, bool scaled)
{
struct drm_i915_private *dev_priv = dev->dev_private;
if (dev_priv->display.update_sprite_wm)
dev_priv->display.update_sprite_wm(dev, pipe, sprite_width,
- pixel_size, enable);
+ pixel_size, enable, scaled);
}
static struct drm_i915_gem_object *