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| author | Daniel Vetter <daniel.vetter@ffwll.ch> | 2012-09-09 11:54:16 +0200 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2012-09-10 21:30:03 +0200 |
| commit | 974a3b0f9f05b748fe11f1afc31efc32aa5160cb (patch) | |
| tree | 67c4ad2aba294c941bfd10d68b4b2e889c041dc4 /drivers/gpu/drm/i915/intel_pm.c | |
| parent | 99d0b1db6ccd0c0e554398e8a579ff3dd4d119ee (diff) | |
| download | lwn-974a3b0f9f05b748fe11f1afc31efc32aa5160cb.tar.gz lwn-974a3b0f9f05b748fe11f1afc31efc32aa5160cb.zip | |
drm/i915: set the right gen3 flip_done mode also at resume
Currently we've only frobbed this bit at irq_init time, but did
not restore it at resume time. Move it to the gen3 clock gating
function to fix this.
Notice while reading through code.
Cc: stable@vger.kernel.org (for 3.5 only)
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_pm.c')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_pm.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 1881c8c83f0e..ba8a27b1757a 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -3672,6 +3672,9 @@ static void gen3_init_clock_gating(struct drm_device *dev) if (IS_PINEVIEW(dev)) I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY)); + + /* IIR "flip pending" means done if this bit is set */ + I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE)); } static void i85x_init_clock_gating(struct drm_device *dev) |