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authorVille Syrjälä <ville.syrjala@linux.intel.com>2014-11-07 21:33:45 +0200
committerDaniel Vetter <daniel.vetter@ffwll.ch>2014-11-17 15:30:55 +0100
commit8d40c3ae51483059733187ba8bc6e031764fafec (patch)
tree3752539da66f52b7954c5f30fa85f1b9b1b996ff /drivers/gpu/drm/i915/intel_pm.c
parentc8e9627d2ad9efed125bcee8587ea27889fb06d2 (diff)
downloadlwn-8d40c3ae51483059733187ba8bc6e031764fafec.tar.gz
lwn-8d40c3ae51483059733187ba8bc6e031764fafec.zip
drm/i915: Warn if GPLL isn't used on vlv/chv
Our freq<->opcode conversions assume that GPLL is always used. Apparently that should be the case always, but let's scream if we ever encounter something different. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Deepak S<deepak.s@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_pm.c')
-rw-r--r--drivers/gpu/drm/i915/intel_pm.c6
1 files changed, 6 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 1f2441ffa6e4..cbf84cc84e55 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -5333,6 +5333,9 @@ static void cherryview_enable_rps(struct drm_device *dev)
val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
+ /* RPS code assumes GPLL is used */
+ WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
+
DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & GPLLENABLE ? "yes" : "no");
DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
@@ -5413,6 +5416,9 @@ static void valleyview_enable_rps(struct drm_device *dev)
val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
+ /* RPS code assumes GPLL is used */
+ WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
+
DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & GPLLENABLE ? "yes" : "no");
DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);