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| author | Ben Widawsky <ben@bwidawsk.net> | 2013-11-02 21:07:58 -0700 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2013-11-08 18:10:05 +0100 |
| commit | 7f88da0cf6947c3b6a5ccad6c37336367dd69159 (patch) | |
| tree | 2bbdad4f12a3ec63aa9b5c9066df59c32408516c /drivers/gpu/drm/i915/intel_pm.c | |
| parent | bf66347cd3a3e947d4eff5bafa6c72283c2411ed (diff) | |
| download | lwn-7f88da0cf6947c3b6a5ccad6c37336367dd69159.tar.gz lwn-7f88da0cf6947c3b6a5ccad6c37336367dd69159.zip | |
drm/i915/bdw: Limit SDE poly depth FIFO to 2
BDW-A workaround
BDW Bug #1899155
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_pm.c')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_pm.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 7e0039e8c2d4..5dceb56f6ceb 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -5294,6 +5294,9 @@ static void gen8_init_clock_gating(struct drm_device *dev) _MASKED_BIT_ENABLE(GEN8_SAMPLER_POWER_BYPASS_DIS)); I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_BWGTLB_DISABLE)); + I915_WRITE(_3D_CHICKEN3, + _3D_CHICKEN_SDE_LIMIT_FIFO_POLY_DEPTH(2)); + /* WaSwitchSolVfFArbitrationPriority */ I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL); |