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| author | Damien Lespiau <damien.lespiau@intel.com> | 2014-03-26 18:18:01 +0000 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2014-09-24 14:57:29 +0200 |
| commit | 3ca5da43003a5bd0ef1d4c15d015c77411e0df0d (patch) | |
| tree | ba8ff2def9196682334d9ec9bac8c1a2636ae015 /drivers/gpu/drm/i915/intel_pm.c | |
| parent | 91e41d1665c868a26a24580b83c321e04be43dfe (diff) | |
| download | lwn-3ca5da43003a5bd0ef1d4c15d015c77411e0df0d.tar.gz lwn-3ca5da43003a5bd0ef1d4c15d015c77411e0df0d.zip | |
drm/i915/skl: Implement WaDisableDgMirrorFixInHalfSliceChicken5:skl
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_pm.c')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_pm.c | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 64eb3b82b466..4f5dcf545c89 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -77,6 +77,14 @@ static void gen9_init_clock_gating(struct drm_device *dev) I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) | GEN8_SDEUNIT_CLOCK_GATE_DISABLE); + /* + * WaDisableDgMirrorFixInHalfSliceChicken5:skl + * This is a pre-production w/a. + */ + I915_WRITE(GEN9_HALF_SLICE_CHICKEN5, + I915_READ(GEN9_HALF_SLICE_CHICKEN5) & + ~GEN9_DG_MIRROR_FIX_ENABLE); + /* Wa4x4STCOptimizationDisable:skl */ I915_WRITE(CACHE_MODE_1, _MASKED_BIT_ENABLE(GEN8_4x4_STC_OPTIMIZATION_DISABLE)); |