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| author | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2014-02-04 21:59:21 +0200 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2014-03-04 15:39:24 +0100 |
| commit | 36075a4cad5adab51a97f32abf41db00975cabd9 (patch) | |
| tree | fd7af0a5b3a4be3da79f698cd32e2d518cacf972 /drivers/gpu/drm/i915/intel_pm.c | |
| parent | a12c4967c96a41cbfc95a8cf8bc7bd697d9df054 (diff) | |
| download | lwn-36075a4cad5adab51a97f32abf41db00975cabd9.tar.gz lwn-36075a4cad5adab51a97f32abf41db00975cabd9.zip | |
drm/i915: Change BDW WIZ hashing mode to 16x4
BSpec recommends using 8x4 hashing mode when MSAA is used. But in
practice 16x4 seems to have a slight edge in performance (on IVB and
HSW at least). So just use 16x4.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Antti Koskipää <antti.koskipaa@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_pm.c')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_pm.c | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 7da7360fea35..151afe53cc7c 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -4843,6 +4843,13 @@ static void gen8_init_clock_gating(struct drm_device *dev) I915_WRITE(GEN7_FF_THREAD_MODE, I915_READ(GEN7_FF_THREAD_MODE) & ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME)); + + /* + * BSpec recommends 8x4 when MSAA is used, + * however in practice 16x4 seems fastest. + */ + I915_WRITE(GEN7_GT_MODE, + GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4); } static void haswell_init_clock_gating(struct drm_device *dev) |