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| author | Akash Goel <akash.goel@intel.com> | 2015-03-06 11:07:17 +0530 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2015-03-17 22:30:23 +0100 |
| commit | 5704195c3f3c04a00c16334a033b180f16db1f94 (patch) | |
| tree | 2deaa791e740bebe767fe0c1d75081cf9956e8d9 /drivers/gpu/drm/i915/intel_pm.c | |
| parent | cee991cb9323995b5c1e5f39540b6055ca5e73e4 (diff) | |
| download | lwn-5704195c3f3c04a00c16334a033b180f16db1f94.tar.gz lwn-5704195c3f3c04a00c16334a033b180f16db1f94.zip | |
drm/i915/skl: Updated the gen6_set_rps function
On SKL, the frequency is programmed differently in RPNSWREQ (A008)
register (from bits 23 to 31, compared to bits 24 to 31). So updated
the gen6_set_rps function, as per this change.
Signed-off-by: Akash Goel <akash.goel@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_pm.c')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_pm.c | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index f240e8578e00..1f5583dc7e6f 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -3947,7 +3947,10 @@ static void gen6_set_rps(struct drm_device *dev, u8 val) if (val != dev_priv->rps.cur_freq) { gen6_set_rps_thresholds(dev_priv, val); - if (IS_HASWELL(dev) || IS_BROADWELL(dev)) + if (IS_GEN9(dev)) + I915_WRITE(GEN6_RPNSWREQ, + GEN9_FREQUENCY(val)); + else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) I915_WRITE(GEN6_RPNSWREQ, HSW_FREQUENCY(val)); else |