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authorDaniel Vetter <daniel.vetter@ffwll.ch>2013-04-24 11:13:35 +0200
committerDaniel Vetter <daniel.vetter@ffwll.ch>2013-04-24 13:06:01 +0200
commitfd0c06420d39958032655a04cfd194d5a7b38f83 (patch)
treec3c6c25b1a06a1f4b201f071375c3ef797fc02f7 /drivers/gpu/drm/i915/intel_pm.c
parentd20d4f0ca343c0b76567d46fcc343c165e8d7c43 (diff)
downloadlwn-fd0c06420d39958032655a04cfd194d5a7b38f83.tar.gz
lwn-fd0c06420d39958032655a04cfd194d5a7b38f83.zip
drm/i915: disable interrupts earlier in the driver unload code
Our rps code relies on the interrupts being off to prevent re-arming of the work items at inopportune moments. Also drop the redundant cancel_work for the main rps work, disable_gt_powersave already takes care of that. Finally add a WARN_ON to ensure we obey that piece of ordering constraint. Long term I want to lock down the setup/teardown code in a similar way to how we painstakingly check modeset sequence constraints already. v2: Disable polling after hpd handling is shut down - since Egbert's hpd irq storm handling the hotplug work can re-arm the polling handler. Spotted by Jani Nikula. Cc: Jesse Barnes <jbarnes@virtuousgeek.org> Cc: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_pm.c')
-rw-r--r--drivers/gpu/drm/i915/intel_pm.c3
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 8b7f050decdd..bb45122173dd 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3671,6 +3671,9 @@ void intel_disable_gt_powersave(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev->dev_private;
+ /* Interrupts should be disabled already to avoid re-arming. */
+ WARN_ON(dev->irq_enabled);
+
if (IS_IRONLAKE_M(dev)) {
ironlake_disable_drps(dev);
ironlake_disable_rc6(dev);