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authorBen Widawsky <benjamin.widawsky@intel.com>2014-01-28 20:25:40 -0800
committerDaniel Vetter <daniel.vetter@ffwll.ch>2014-02-12 18:53:13 +0100
commit1c79b42fa508bb49db57033e45711239b1fe96e9 (patch)
treefb10d43587337cb1d86e55c367085dcf9c44f409 /drivers/gpu/drm/i915/intel_pm.c
parent8bade1adc7459a9283eb93a4b312289ecdad1690 (diff)
downloadlwn-1c79b42fa508bb49db57033e45711239b1fe96e9.tar.gz
lwn-1c79b42fa508bb49db57033e45711239b1fe96e9.zip
drm/i915: Just print rc6 facts
Everything can be overridden by module parameters, so don't confuse the users that are using them. We have RC6 turned on for all platforms which support it, but Ironlake, so the need to explain the situation is no longer pressing. Signed-off-by: Ben Widawsky <ben@bwidawsk.net> Reviewed-by: Deepak S <deepak.s@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_pm.c')
-rw-r--r--drivers/gpu/drm/i915/intel_pm.c12
1 files changed, 3 insertions, 9 deletions
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 8f8d84005779..2edb8c77013e 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3196,16 +3196,10 @@ static void valleyview_disable_rps(struct drm_device *dev)
static void intel_print_rc6_info(struct drm_device *dev, u32 mode)
{
- if (IS_GEN6(dev))
- DRM_DEBUG_DRIVER("Sandybridge: deep RC6 disabled\n");
-
- if (IS_HASWELL(dev))
- DRM_DEBUG_DRIVER("Haswell: only RC6 available\n");
-
DRM_INFO("Enabling RC6 states: RC6 %s, RC6p %s, RC6pp %s\n",
- (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off",
- (mode & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off",
- (mode & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off");
+ (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off",
+ (mode & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off",
+ (mode & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off");
}
int intel_enable_rc6(const struct drm_device *dev)