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| author | Imre Deak <imre.deak@intel.com> | 2015-09-03 16:24:35 +0300 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2015-09-04 10:18:45 +0200 |
| commit | c5796b7126b2497513bfa9a9341d02cb833d83d6 (patch) | |
| tree | 68ebcf4ebbfdc85abaead03082e32e15f32f81d7 /drivers/gpu/drm/i915/intel_lvds.c | |
| parent | 01101fa7cc85fffc95798d1f67970dad96063fc6 (diff) | |
| download | lwn-c5796b7126b2497513bfa9a9341d02cb833d83d6.tar.gz lwn-c5796b7126b2497513bfa9a9341d02cb833d83d6.zip | |
drm/i915: access the PP_CONTROL reg only pre GEN5
This register exists only pre GEN5, but atm we also access it on
VLV/BXT/CHV. Prevent accessing it on these latter platforms.
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_lvds.c')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_lvds.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/intel_lvds.c b/drivers/gpu/drm/i915/intel_lvds.c index 0794dc84ff01..a16308ad9124 100644 --- a/drivers/gpu/drm/i915/intel_lvds.c +++ b/drivers/gpu/drm/i915/intel_lvds.c @@ -955,7 +955,7 @@ void intel_lvds_init(struct drm_device *dev) if (HAS_PCH_SPLIT(dev)) { I915_WRITE(PCH_PP_CONTROL, I915_READ(PCH_PP_CONTROL) | PANEL_UNLOCK_REGS); - } else { + } else if (INTEL_INFO(dev_priv)->gen < 5) { I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) | PANEL_UNLOCK_REGS); } |