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author | Paulo Zanoni <paulo.r.zanoni@intel.com> | 2015-02-13 17:23:42 -0200 |
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committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2015-02-23 23:59:39 +0100 |
commit | 68b92147d53ad5a6fd59ab066210b988faf5a3c7 (patch) | |
tree | c65607a98de17948d05f8b178c9eec05c61d2490 /drivers/gpu/drm/i915/intel_fbc.c | |
parent | 95106753878fc3e60dde6346a71f4d0cb388cb48 (diff) | |
download | lwn-68b92147d53ad5a6fd59ab066210b988faf5a3c7.tar.gz lwn-68b92147d53ad5a6fd59ab066210b988faf5a3c7.zip |
drm/i915: HSW+ FBC is tied to pipe A
So add code to consider this case.
v2: Reorder the series, so drop the possible_framebuffer_bits chunk.
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> (v1)
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_fbc.c')
-rw-r--r-- | drivers/gpu/drm/i915/intel_fbc.c | 13 |
1 files changed, 11 insertions, 2 deletions
diff --git a/drivers/gpu/drm/i915/intel_fbc.c b/drivers/gpu/drm/i915/intel_fbc.c index 69342d0501e9..6406b1432a2e 100644 --- a/drivers/gpu/drm/i915/intel_fbc.c +++ b/drivers/gpu/drm/i915/intel_fbc.c @@ -475,10 +475,16 @@ static bool set_no_fbc_reason(struct drm_i915_private *dev_priv, static struct drm_crtc *intel_fbc_find_crtc(struct drm_i915_private *dev_priv) { - struct drm_device *dev = dev_priv->dev; struct drm_crtc *crtc = NULL, *tmp_crtc; + enum pipe pipe; + bool pipe_a_only = false; + + if (IS_HASWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 8) + pipe_a_only = true; + + for_each_pipe(dev_priv, pipe) { + tmp_crtc = dev_priv->pipe_to_crtc_mapping[pipe]; - for_each_crtc(dev, tmp_crtc) { if (intel_crtc_active(tmp_crtc) && to_intel_crtc(tmp_crtc)->primary_enabled) { if (crtc) { @@ -488,6 +494,9 @@ static struct drm_crtc *intel_fbc_find_crtc(struct drm_i915_private *dev_priv) } crtc = tmp_crtc; } + + if (pipe_a_only) + break; } if (!crtc || crtc->primary->fb == NULL) { |