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| author | Chon Ming Lee <chon.ming.lee@intel.com> | 2013-09-04 01:30:38 +0800 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2013-09-04 17:34:58 +0200 |
| commit | 65ce4bf5a15fcd4d15898be47795d0550eb2325c (patch) | |
| tree | 3b2ce08e8e1c034921ef83dc401d0876fb13cce0 /drivers/gpu/drm/i915/intel_dp.c | |
| parent | 9dd4ffdf3936e9cd85a5c856a192134b23b4b2ac (diff) | |
| download | lwn-65ce4bf5a15fcd4d15898be47795d0550eb2325c.tar.gz lwn-65ce4bf5a15fcd4d15898be47795d0550eb2325c.zip | |
drm/i915: Move Valleyview DP DPLL divisor calc to intel_dp_set_clock v2
For DP pll settings, there is only two golden configs. Instead of
running through the algorithm to determine it, hardcode the value and get it
determine in intel_dp_set_clock.
v2: Rework on the intel_limit compiler warning. (Jani)
Signed-off-by: Chon Ming Lee <chon.ming.lee@intel.com>
[danvet: Fix up checkpatch issues.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_dp.c')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_dp.c | 10 |
1 files changed, 9 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index c256ddd31e9b..c192dbb8a36c 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -57,6 +57,13 @@ static const struct dp_link_dpll pch_dpll[] = { { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } } }; +static const struct dp_link_dpll vlv_dpll[] = { + { DP_LINK_BW_1_62, + { .p1 = 3, .p2 = 2, .n = 5, .m1 = 5, .m2 = 3 } }, + { DP_LINK_BW_2_7, + { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } } +}; + /** * is_edp - is the given port attached to an eDP panel (either CPU or PCH) * @intel_dp: DP struct @@ -680,7 +687,8 @@ intel_dp_set_clock(struct intel_encoder *encoder, divisor = pch_dpll; count = ARRAY_SIZE(pch_dpll); } else if (IS_VALLEYVIEW(dev)) { - /* FIXME: Need to figure out optimized DP clocks for vlv. */ + divisor = vlv_dpll; + count = ARRAY_SIZE(vlv_dpll); } if (divisor && count) { |