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| author | Daniel Vetter <daniel.vetter@ffwll.ch> | 2012-10-20 20:57:44 +0200 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2012-10-24 17:54:36 +0200 |
| commit | 6b3ec1c9fb73cca38842d030b171ffd16a686949 (patch) | |
| tree | 6d71b706e055498d16c11ce5e340a35a82fde6f3 /drivers/gpu/drm/i915/intel_dp.c | |
| parent | d2acd215cdb75eb39afadbf31a19bdcf84af7eaf (diff) | |
| download | lwn-6b3ec1c9fb73cca38842d030b171ffd16a686949.tar.gz lwn-6b3ec1c9fb73cca38842d030b171ffd16a686949.zip | |
drm/i915/dp: compute the pch dp aux divider from the rawclk
Otherwise dp aux won't work on some hsw platforms, since they use a
different rawclk than the 125MHz clock used thus far.
To absolutely not change anything, round up: That way we get the old
63 divider for the default 125MHz clock.
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Tested-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_dp.c')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_dp.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index adfb98cb7ba9..c1ed1aff2750 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -377,7 +377,7 @@ intel_dp_aux_ch(struct intel_dp *intel_dp, else aux_clock_divider = 225; /* eDP input clock at 450Mhz */ } else if (HAS_PCH_SPLIT(dev)) - aux_clock_divider = 63; /* IRL input clock fixed at 125Mhz */ + aux_clock_divider = DIV_ROUND_UP(intel_pch_rawclk(dev), 2); else aux_clock_divider = intel_hrawclk(dev) / 2; |