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| author | Adam Jackson <ajax@redhat.com> | 2011-07-12 17:38:05 -0400 |
|---|---|---|
| committer | Keith Packard <keithp@keithp.com> | 2011-07-25 10:35:07 -0700 |
| commit | a2cab1b24a4ea75a68fa21bfb7d5b1a45121583c (patch) | |
| tree | 89adf71ab7b590df8835718a8ed7bea792798259 /drivers/gpu/drm/i915/intel_dp.c | |
| parent | 71ba9000e673d6171a52f2a8b14e0419087f7199 (diff) | |
| download | lwn-a2cab1b24a4ea75a68fa21bfb7d5b1a45121583c.tar.gz lwn-a2cab1b24a4ea75a68fa21bfb7d5b1a45121583c.zip | |
drm/i915/dp: Explicitly request 8/10 channel coding
It's not clear what a sink would do if you wrote zero to this register -
which I guess would mean "I don't support any channel encodings, good
luck" - but let's not find out.
Signed-off-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Keith Packard <keithp@keithp.com>
Signed-off-by: Keith Packard <keithp@keithp.com>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_dp.c')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_dp.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 9a0c3ca1ffa9..1c3a36feaf69 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -769,6 +769,7 @@ intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode, memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE); intel_dp->link_configuration[0] = intel_dp->link_bw; intel_dp->link_configuration[1] = intel_dp->lane_count; + intel_dp->link_configuration[8] = DP_SET_ANSI_8B10B; /* * Check for DPCD version > 1.1 and enhanced framing support |