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authorChris Wilson <chris@chris-wilson.co.uk>2010-11-11 17:54:52 +0000
committerChris Wilson <chris@chris-wilson.co.uk>2010-11-11 17:54:52 +0000
commit8168bd48bb863c00747497aadf13884b2d69d287 (patch)
tree17159818d70ec4e313d01b280f51be6afa70236f /drivers/gpu/drm/i915/intel_display.c
parente74cfed521746544e6eeee84b24bd31c1e59ffe2 (diff)
downloadlwn-8168bd48bb863c00747497aadf13884b2d69d287.tar.gz
lwn-8168bd48bb863c00747497aadf13884b2d69d287.zip
drm/i915: Remove the definitions for Primary Ring Buffer
We only ever used the PRB0, neglecting the secondary ring buffers, and now with the advent of multiple engines with separate ring buffers we need to excise the anachronisms from our code (and be explicit about which ring we mean where). This is doubly important in light of the FORCEWAKE required to read ring buffer registers on SandyBridge. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_display.c')
-rw-r--r--drivers/gpu/drm/i915/intel_display.c10
1 files changed, 5 insertions, 5 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 63770c963077..6a7f11ff66f5 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1983,17 +1983,17 @@ static void intel_flush_display_plane(struct drm_device *dev,
static void intel_clear_scanline_wait(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev->dev_private;
+ struct intel_ring_buffer *ring;
u32 tmp;
if (IS_GEN2(dev))
/* Can't break the hang on i8xx */
return;
- tmp = I915_READ(PRB0_CTL);
- if (tmp & RING_WAIT) {
- I915_WRITE(PRB0_CTL, tmp);
- POSTING_READ(PRB0_CTL);
- }
+ ring = &dev_priv->render_ring;
+ tmp = I915_READ_CTL(ring);
+ if (tmp & RING_WAIT)
+ I915_WRITE_CTL(ring, tmp);
}
static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)