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authorJesse Barnes <jbarnes@virtuousgeek.org>2011-07-27 11:51:40 -0700
committerKeith Packard <keithp@keithp.com>2011-07-28 16:28:21 -0700
commit3bcf603f6d5d18bd9d076dc280de71f48add4101 (patch)
tree6d1ed198fd759d3e7aeccd32bc8b5059785da26a /drivers/gpu/drm/i915/intel_display.c
parent120eced9efe7fdb5123db4ea47e9adee9b66284e (diff)
downloadlwn-3bcf603f6d5d18bd9d076dc280de71f48add4101.tar.gz
lwn-3bcf603f6d5d18bd9d076dc280de71f48add4101.zip
drm/i915: apply timing generator bug workaround on CPT and PPT
On CougarPoint and PantherPoint PCH chips, the timing generator may fail to start after DP training completes. This is due to a bug in the FDI autotraining detect logic (which will stall the timing generator and re-enable it once training completes), so disable it to avoid silent DP mode setting failures. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Keith Packard <keithp@keithp.com>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_display.c')
-rw-r--r--drivers/gpu/drm/i915/intel_display.c4
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index d9b8c15998d9..502efc37b074 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -7524,6 +7524,7 @@ static void ibx_init_clock_gating(struct drm_device *dev)
static void cpt_init_clock_gating(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev->dev_private;
+ int pipe;
/*
* On Ibex Peak and Cougar Point, we need to disable clock
@@ -7533,6 +7534,9 @@ static void cpt_init_clock_gating(struct drm_device *dev)
I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
DPLS_EDP_PPS_FIX_DIS);
+ /* Without this, mode sets may fail silently on FDI */
+ for_each_pipe(pipe)
+ I915_WRITE(TRANS_CHICKEN2(pipe), TRANS_AUTOTRAIN_GEN_STALL_DIS);
}
static void ironlake_teardown_rc6(struct drm_device *dev)