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authorImre Deak <imre.deak@intel.com>2015-03-17 11:40:05 +0200
committerDaniel Vetter <daniel.vetter@ffwll.ch>2015-03-20 11:48:21 +0100
commit9ca3ba011b9f1bf7fc73a4e7dc0c9edec2aeb149 (patch)
treeb7477fb4f93446b6e6a754797522dcec5250a491 /drivers/gpu/drm/i915/intel_display.c
parent24be4e4650de2fc323ee0737f945ad366b6c11cc (diff)
downloadlwn-9ca3ba011b9f1bf7fc73a4e7dc0c9edec2aeb149.tar.gz
lwn-9ca3ba011b9f1bf7fc73a4e7dc0c9edec2aeb149.zip
drm/i915/chv: use vlv_PLL_is_optimal in chv_find_best_dpll
Prepare chv_find_best_dpll to be used for BXT too, where we want to consider the error between target and calculated frequency too when choosing a better PLL configuration. No functional change. Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_display.c')
-rw-r--r--drivers/gpu/drm/i915/intel_display.c26
1 files changed, 20 insertions, 6 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index b0aa6a4784c4..60230dcf532f 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -786,6 +786,16 @@ static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
unsigned int best_error_ppm,
unsigned int *error_ppm)
{
+ /*
+ * For CHV ignore the error and consider only the P value.
+ * Prefer a bigger P value based on HW requirements.
+ */
+ if (IS_CHERRYVIEW(dev)) {
+ *error_ppm = 0;
+
+ return calculated_clock->p > best_clock->p;
+ }
+
if (WARN_ON_ONCE(!target_freq))
return false;
@@ -864,11 +874,13 @@ chv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
intel_clock_t *best_clock)
{
struct drm_device *dev = crtc->base.dev;
+ unsigned int best_error_ppm;
intel_clock_t clock;
uint64_t m2;
int found = false;
memset(best_clock, 0, sizeof(*best_clock));
+ best_error_ppm = 1000000;
/*
* Based on hardware doc, the n always set to 1, and m1 always
@@ -882,6 +894,7 @@ chv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
for (clock.p2 = limit->p2.p2_fast;
clock.p2 >= limit->p2.p2_slow;
clock.p2 -= clock.p2 > 10 ? 2 : 1) {
+ unsigned int error_ppm;
clock.p = clock.p1 * clock.p2;
@@ -898,12 +911,13 @@ chv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
if (!intel_PLL_is_valid(dev, limit, &clock))
continue;
- /* based on hardware requirement, prefer bigger p
- */
- if (clock.p > best_clock->p) {
- *best_clock = clock;
- found = true;
- }
+ if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
+ best_error_ppm, &error_ppm))
+ continue;
+
+ *best_clock = clock;
+ best_error_ppm = error_ppm;
+ found = true;
}
}