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| author | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2014-06-28 02:03:59 +0300 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2014-08-08 17:43:42 +0200 |
| commit | d17ec4ced6c0907f80f51677a44236da94ecd92d (patch) | |
| tree | feb8a6188667c7a62edef67e2d11fab873a482bf /drivers/gpu/drm/i915/intel_display.c | |
| parent | d49a340d6eb6de45c1a886b71469d110f2dbb57b (diff) | |
| download | lwn-d17ec4ced6c0907f80f51677a44236da94ecd92d.tar.gz lwn-d17ec4ced6c0907f80f51677a44236da94ecd92d.zip | |
drm/i915: Leave DPLL ref clocks on
We enable the DPLL refclock already when bringing up the cmnlane power
well, so also leave it on when otherwise disabling the DPLL.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_display.c')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_display.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index a7d0c88a620d..6ca53b372a4c 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -1684,7 +1684,7 @@ static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) assert_pipe_disabled(dev_priv, pipe); /* Set PLL en = 0 */ - val = DPLL_SSC_REF_CLOCK_CHV; + val = DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV; if (pipe != PIPE_A) val |= DPLL_INTEGRATED_CRI_CLK_VLV; I915_WRITE(DPLL(pipe), val); |