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author | Imre Deak <imre.deak@intel.com> | 2013-04-17 14:04:50 +0300 |
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committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2013-05-10 21:56:35 +0200 |
commit | 7d708ee40a6b9ca1112a322e554c887df105b025 (patch) | |
tree | ce5a29a139c6e6c1c0c2d3e156ba3f8f48800baf /drivers/gpu/drm/i915/intel_display.c | |
parent | bc5ead8c09b51e85d110132495a9bfa58dc39dab (diff) | |
download | lwn-7d708ee40a6b9ca1112a322e554c887df105b025.tar.gz lwn-7d708ee40a6b9ca1112a322e554c887df105b025.zip |
drm/i915: HSW: allow PCH clock gating for suspend
For the device to enter D3 we should enable PCH clock gating.
v2:
- use HAS_PCH_LPT instead of IS_HASWELL (Ville, Paolo)
- rename lpt_allow_clock_gating to lpt_suspend_hw (Paolo)
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_display.c')
-rw-r--r-- | drivers/gpu/drm/i915/intel_display.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index f5523a80efc9..b89072252b6c 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -9271,6 +9271,11 @@ void intel_modeset_init_hw(struct drm_device *dev) mutex_unlock(&dev->struct_mutex); } +void intel_modeset_suspend_hw(struct drm_device *dev) +{ + intel_suspend_hw(dev); +} + void intel_modeset_init(struct drm_device *dev) { struct drm_i915_private *dev_priv = dev->dev_private; |