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| author | Damien Lespiau <damien.lespiau@intel.com> | 2015-06-04 18:21:31 +0100 |
|---|---|---|
| committer | Jani Nikula <jani.nikula@intel.com> | 2015-06-12 13:14:36 +0300 |
| commit | 414355a7c3f029b762518d73a6ea7e4d07d48e34 (patch) | |
| tree | 467a071fffe91d21ba36588a71306e2663f82c92 /drivers/gpu/drm/i915/intel_display.c | |
| parent | a9419e846bd8c8e00c1d28282de936523229eff7 (diff) | |
| download | lwn-414355a7c3f029b762518d73a6ea7e4d07d48e34.tar.gz lwn-414355a7c3f029b762518d73a6ea7e4d07d48e34.zip | |
drm/i915/skl: Don't warn if reading back DPLL0 is disabled
We can operate with DPLL0 off with CDCLK backed by the 24Mhz reference
clock, and that's a supported configuration. Don't warn when notice
DPLL0 is off then.
We still have a separate warn at boot if cdclk is disabled (because we
don't currently try to handle the case (that shouldn't happen on SKL as
far as I know) where we boot with display not initialized.
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_display.c')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_display.c | 4 |
1 files changed, 1 insertions, 3 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 9280e76505fc..0a3456988c12 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -6737,10 +6737,8 @@ static int skylake_get_display_clock_speed(struct drm_device *dev) uint32_t cdctl = I915_READ(CDCLK_CTL); uint32_t linkrate; - if (!(lcpll1 & LCPLL_PLL_ENABLE)) { - WARN(1, "LCPLL1 not enabled\n"); + if (!(lcpll1 & LCPLL_PLL_ENABLE)) return 24000; /* 24MHz is the cd freq with NSSC ref */ - } if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540) return 540000; |