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| author | Vinod Govindapillai <vinod.govindapillai@intel.com> | 2023-03-23 13:44:25 +0200 |
|---|---|---|
| committer | Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> | 2023-03-27 15:58:28 +0300 |
| commit | ff168b37a96736c892007730e703e74d5a23ca48 (patch) | |
| tree | abb74e94639aaeb01a22997369582988b36a360d /drivers/gpu/drm/i915/i915_reg.h | |
| parent | 419e505dab203b85facc782ec34d2d98601644ff (diff) | |
| download | lwn-ff168b37a96736c892007730e703e74d5a23ca48.tar.gz lwn-ff168b37a96736c892007730e703e74d5a23ca48.zip | |
drm/i915/reg: fix QGV points register access offsets
Wrong offsets are calculated to read QGV point registers. Fix it
to read from the correct registers.
Bspec: 64602
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230323114426.41136-2-vinod.govindapillai@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/i915_reg.h')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 0e1e3a6fd1cb..3abfda4c7a3f 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -7748,12 +7748,13 @@ enum skl_power_gate { #define MTL_N_OF_POPULATED_CH_MASK REG_GENMASK(7, 4) #define MTL_DDR_TYPE_MASK REG_GENMASK(3, 0) -#define MTL_MEM_SS_INFO_QGV_POINT_LOW(point) _MMIO(0x45710 + (point) * 2) +#define MTL_MEM_SS_INFO_QGV_POINT_OFFSET 0x45710 +#define MTL_MEM_SS_INFO_QGV_POINT_LOW(point) _MMIO(MTL_MEM_SS_INFO_QGV_POINT_OFFSET + (point) * 8) #define MTL_TRCD_MASK REG_GENMASK(31, 24) #define MTL_TRP_MASK REG_GENMASK(23, 16) #define MTL_DCLK_MASK REG_GENMASK(15, 0) -#define MTL_MEM_SS_INFO_QGV_POINT_HIGH(point) _MMIO(0x45714 + (point) * 2) +#define MTL_MEM_SS_INFO_QGV_POINT_HIGH(point) _MMIO(MTL_MEM_SS_INFO_QGV_POINT_OFFSET + (point) * 8 + 4) #define MTL_TRAS_MASK REG_GENMASK(16, 8) #define MTL_TRDPRE_MASK REG_GENMASK(7, 0) |