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| author | Madhav Chauhan <madhav.chauhan@intel.com> | 2016-12-02 10:23:53 +0200 |
|---|---|---|
| committer | Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com> | 2016-12-02 16:41:47 +0200 |
| commit | f7044dd904d7a97967af097515da272fa89b00e9 (patch) | |
| tree | a7d59379ae480dae359c5be6c2ef5bb1bd6c875d /drivers/gpu/drm/i915/i915_reg.h | |
| parent | 51b3ee35affa3695bd89f6c6cdb22cd65aff5155 (diff) | |
| download | lwn-f7044dd904d7a97967af097515da272fa89b00e9.tar.gz lwn-f7044dd904d7a97967af097515da272fa89b00e9.zip | |
drm/i915/glk: Update Port PLL enable sequence for Geminilkae
Add steps for enabling and disabling Port PLL as per bspec.
Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1480667037-11215-6-git-send-email-ander.conselvan.de.oliveira@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/i915_reg.h')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 6cff01debe72..90685d235410 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1574,6 +1574,8 @@ enum skl_disp_power_wells { #define PORT_PLL_ENABLE (1 << 31) #define PORT_PLL_LOCK (1 << 30) #define PORT_PLL_REF_SEL (1 << 27) +#define PORT_PLL_POWER_ENABLE (1 << 26) +#define PORT_PLL_POWER_STATE (1 << 25) #define BXT_PORT_PLL_ENABLE(port) _MMIO_PORT(port, _PORT_PLL_A, _PORT_PLL_B) #define _PORT_PLL_EBB_0_A 0x162034 |