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| author | Ben Widawsky <ben@bwidawsk.net> | 2012-03-29 19:11:26 -0700 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2012-04-09 18:04:05 +0200 |
| commit | e2a1e2f0242c363ed80458282d67039c373fbb1f (patch) | |
| tree | 7219f4986094a8f86bcb09fe39af1e73199916f8 /drivers/gpu/drm/i915/i915_reg.h | |
| parent | 96d6e3506739c1ca2ebe578eb157dfd504bfad3a (diff) | |
| download | lwn-e2a1e2f0242c363ed80458282d67039c373fbb1f.tar.gz lwn-e2a1e2f0242c363ed80458282d67039c373fbb1f.zip | |
drm/i915: ring irq cleanups
- gen6 put/get only need one argument
rflags and gflags are always the same (see above explanation)
- remove a couple redundantly defined IRQs
- reordered some lines to make things go in descending order
Every ring has its own interrupts, enables, masks, and status bits that
are fed into the main interrupt enable/mask/status registers. At one
point in time it seemed like a good idea to make our functions support
the notion that each interrupt may have a different bit position in the
corresponding register (blitter parser error may be bit n in IMR, but
bit m in blitter IMR). It turned out though that the HW designers did us
a solid on Gen6+ and this unfortunate situation has been avoided. This
allows our interrupt code to be cleaned up a bit.
I jammed this into one commit because there should be no functional
change with this commit, and staging it into multiple commits was
unnecessarily artificial IMO.
CC: Chris Wilson <chris@chris-wilson.co.uk>
CC: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
[danvet:
- fixed up merged conflict with vlv changes.
- added GEN6 to GT blitter bit, we only use it on gen6+.
- added a comment to both ring irq bits and GT irq bits that on gen6+
these alias.
- added comment that GT_BSD_USER_INTERRUPT is ilk-only.
- I've got confused a bit that we still use GT_USER_INTERRUPT on ivb
for the render ring - but this goes back to ilk where we have only
gt interrupt bits and so we be equally confusing if changed.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_reg.h')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 12 |
1 files changed, 8 insertions, 4 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 0f6f567ae507..56d4db8026e3 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -643,7 +643,9 @@ #define CACHE_MODE_1 0x7004 /* IVB+ */ #define PIXEL_SUBSPAN_COLLECT_OPT_DISABLE (1<<6) -/* GEN6 interrupt control */ +/* GEN6 interrupt control + * Note that the per-ring interrupt bits do alias with the global interrupt bits + * in GTIMR. */ #define GEN6_RENDER_HWSTAM 0x2098 #define GEN6_RENDER_IMR 0x20a8 #define GEN6_RENDER_CONTEXT_SWITCH_INTERRUPT (1 << 8) @@ -3203,13 +3205,15 @@ #define DEIIR 0x44008 #define DEIER 0x4400c -/* GT interrupt */ +/* GT interrupt. + * Note that for gen6+ the ring-specific interrupt bits do alias with the + * corresponding bits in the per-ring interrupt control registers. */ #define GT_GEN6_BLT_FLUSHDW_NOTIFY_INTERRUPT (1 << 26) #define GT_GEN6_BLT_CS_ERROR_INTERRUPT (1 << 25) -#define GT_BLT_USER_INTERRUPT (1 << 22) +#define GT_GEN6_BLT_USER_INTERRUPT (1 << 22) #define GT_GEN6_BSD_CS_ERROR_INTERRUPT (1 << 15) #define GT_GEN6_BSD_USER_INTERRUPT (1 << 12) -#define GT_BSD_USER_INTERRUPT (1 << 5) +#define GT_BSD_USER_INTERRUPT (1 << 5) /* ilk only */ #define GT_GEN7_L3_PARITY_ERROR_INTERRUPT (1 << 5) #define GT_PIPE_NOTIFY (1 << 4) #define GT_RENDER_CS_ERROR_INTERRUPT (1 << 3) |