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authorVille Syrjälä <ville.syrjala@linux.intel.com>2019-07-18 17:50:53 +0300
committerVille Syrjälä <ville.syrjala@linux.intel.com>2019-09-20 21:46:24 +0300
commitd1844606fd63af1994e153a8607d4b13709bc395 (patch)
tree546b004d5d371b7df1964c9b3300201c250565b2 /drivers/gpu/drm/i915/i915_reg.h
parentaf28cc4c289600ad05da85e466517757a26ce216 (diff)
downloadlwn-d1844606fd63af1994e153a8607d4b13709bc395.tar.gz
lwn-d1844606fd63af1994e153a8607d4b13709bc395.zip
drm/i915: Add PIPECONF YCbCr 4:4:4 programming for ILK-IVB
On ILK-IVB the pipe colorspace is configured via PIPECONF (as opposed to PIPEMISC in BDW+). Let's configure+readout that stuff correctly. Enabling YCbCr 4:4:4 output will now be a simple matter of setting crtc_state->output_format appropriately in the encoder .compute_config(). However, when we do that we must be aware of the fact that YCbCr DP output doesn't seem to work on ILK (resulting image is totally garbled), but on SNB+ it works fine. However HDMI YCbCr output does work correctly even on ILK. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190718145053.25808-13-ville.syrjala@linux.intel.com Reviewed-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_reg.h')
-rw-r--r--drivers/gpu/drm/i915/i915_reg.h4
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 90c45fee9ce7..acbda6d89a9b 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5683,6 +5683,10 @@ enum {
#define PIPECONF_CXSR_DOWNCLOCK (1 << 16)
#define PIPECONF_EDP_RR_MODE_SWITCH_VLV (1 << 14)
#define PIPECONF_COLOR_RANGE_SELECT (1 << 13)
+#define PIPECONF_OUTPUT_COLORSPACE_MASK (3 << 11) /* ilk-ivb */
+#define PIPECONF_OUTPUT_COLORSPACE_RGB (0 << 11) /* ilk-ivb */
+#define PIPECONF_OUTPUT_COLORSPACE_YUV601 (1 << 11) /* ilk-ivb */
+#define PIPECONF_OUTPUT_COLORSPACE_YUV709 (2 << 11) /* ilk-ivb */
#define PIPECONF_OUTPUT_COLORSPACE_YUV_HSW (1 << 11) /* hsw only */
#define PIPECONF_BPC_MASK (0x7 << 5)
#define PIPECONF_8BPC (0 << 5)