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| author | Matt Roper <matthew.d.roper@intel.com> | 2021-08-05 09:36:44 -0700 |
|---|---|---|
| committer | Matt Roper <matthew.d.roper@intel.com> | 2021-08-12 16:07:16 -0700 |
| commit | ad482232e3cc6d65eaeb19ce2412887458b19559 (patch) | |
| tree | 5da858b8dc5286ca65c7d1c1889b601102576e48 /drivers/gpu/drm/i915/i915_reg.h | |
| parent | efd330b97855013c8b58185683ddfb75deab5fa9 (diff) | |
| download | lwn-ad482232e3cc6d65eaeb19ce2412887458b19559.tar.gz lwn-ad482232e3cc6d65eaeb19ce2412887458b19559.zip | |
drm/i915/xehpsdv: Read correct RP_STATE_CAP register
The RP_STATE_CAP register is no longer part of the MCHBAR on XEHPSDV; this
register is now a per-tile register at GTTMMADDR offset 0x250014.
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210805163647.801064-7-matthew.d.roper@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/i915_reg.h')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index c8db6e8ef1ad..f79f02ee12db 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -4124,6 +4124,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) #define RPN_CAP_MASK REG_GENMASK(23, 16) #define BXT_RP_STATE_CAP _MMIO(0x138170) #define GEN9_RP_STATE_LIMITS _MMIO(0x138148) +#define XEHPSDV_RP_STATE_CAP _MMIO(0x250014) /* * Logical Context regs |