diff options
| author | Michel Thierry <michel.thierry@intel.com> | 2019-08-23 01:20:34 -0700 |
|---|---|---|
| committer | Lucas De Marchi <lucas.demarchi@intel.com> | 2019-08-23 10:08:55 -0700 |
| commit | 5d86923060fce88a4dda8d8c9c5d5eb32f37c37b (patch) | |
| tree | 7cc89bd6dcca1d18158b97dd87b9de85032ddfaf /drivers/gpu/drm/i915/i915_reg.h | |
| parent | b3c0692f36a44bd02ee8ccc5bed972a36fbf2e99 (diff) | |
| download | lwn-5d86923060fce88a4dda8d8c9c5d5eb32f37c37b.tar.gz lwn-5d86923060fce88a4dda8d8c9c5d5eb32f37c37b.zip | |
drm/i915/tgl: Enable VD HCP/MFX sub-pipe power gating
HCP/MFX power gating is disabled by default, turn it on for the vd units
available. User space will also issue a MI_FORCE_WAKEUP properly to
wake up proper subwell.
During driver load, init_clock_gating happens after device_info_init_mmio
read the vdbox disable fuse register, so only present vd units will have
these enabled.
BSpec: 14214
HSDES: 1209977827
Signed-off-by: Michel Thierry <michel.thierry@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Tony Ye <tony.ye@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190823082055.5992-3-lucas.demarchi@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/i915_reg.h')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index a092b34c269d..02e1ef10c47e 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -8615,6 +8615,10 @@ enum { #define GEN9_PWRGT_MEDIA_STATUS_MASK (1 << 0) #define GEN9_PWRGT_RENDER_STATUS_MASK (1 << 1) +#define POWERGATE_ENABLE _MMIO(0xa210) +#define VDN_HCP_POWERGATE_ENABLE(n) BIT(((n) * 2) + 3) +#define VDN_MFX_POWERGATE_ENABLE(n) BIT(((n) * 2) + 4) + #define GTFIFODBG _MMIO(0x120000) #define GT_FIFO_SBDEDICATE_FREE_ENTRY_CHV (0x1f << 20) #define GT_FIFO_FREE_ENTRIES_CHV (0x7f << 13) |