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| author | Zou Nan hai <nanhai.zou@intel.com> | 2010-11-09 17:17:32 +0800 |
|---|---|---|
| committer | Chris Wilson <chris@chris-wilson.co.uk> | 2010-11-11 17:45:54 +0000 |
| commit | cae5852dcaa1139b198e13ebd3aeb7f3c065f875 (patch) | |
| tree | 7a6789974c1e5d2f76cf21fb6c8fd1df8711c2ab /drivers/gpu/drm/i915/i915_reg.h | |
| parent | 527f9e907c39f7e88abb57eaa8bccb43c8706a3d (diff) | |
| download | lwn-cae5852dcaa1139b198e13ebd3aeb7f3c065f875.tar.gz lwn-cae5852dcaa1139b198e13ebd3aeb7f3c065f875.zip | |
drm/i915/ringbuffer: set FORCE_WAKE bit before reading ring register
Before reading ring register, set FORCE_WAKE bit to prevent GT core
power down to low power state, otherwise we may read stale values.
Signed-off-by: Zou Nan hai <nanhai.zou@intel.com>
[ickle: added a udelay which seemed to do the trick on my SNB]
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_reg.h')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 61fe2619bb63..1eca8e710b9e 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -3077,4 +3077,5 @@ #define EDP_LINK_TRAIN_800MV_0DB_SNB_B (0x38<<22) #define EDP_LINK_TRAIN_VOL_EMP_MASK_SNB (0x3f<<22) +#define FORCEWAKE 0xA18C #endif /* _I915_REG_H_ */ |