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| author | Damien Lespiau <damien.lespiau@intel.com> | 2014-01-20 16:01:00 +0000 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2014-09-24 14:47:41 +0200 |
| commit | b9ca5fadb3842a7a90934f3ef1795e95b382def1 (patch) | |
| tree | 08402718522d40f0ec960310150ad2b9601a1a69 /drivers/gpu/drm/i915/i915_reg.h | |
| parent | b6b5e38323b276cae53cf34970d968084de701bc (diff) | |
| download | lwn-b9ca5fadb3842a7a90934f3ef1795e95b382def1.tar.gz lwn-b9ca5fadb3842a7a90934f3ef1795e95b382def1.zip | |
drm/i915/skl: Provide a get_aux_send_ctl() vfunc for skylake
Skylake doesn't use the pre-charge field now, but, instead, we need to
specify the total number of SYNC pulses for the SYNC phase (pre-charge +
SYNC pattern pules). Let's use the default value (32) for that.
v3: increase DP AUX TX timeout as 400us is not to be used on SKL
apparently (Jesse).
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_reg.h')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 1eaa3411cdb1..d4af99ee3e0a 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -3634,6 +3634,7 @@ enum punit_power_well { #define DP_AUX_CH_CTL_PRECHARGE_TEST (1 << 11) #define DP_AUX_CH_CTL_BIT_CLOCK_2X_MASK (0x7ff) #define DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT 0 +#define DP_AUX_CH_CTL_SYNC_PULSE_SKL(c) ((c) - 1) /* * Computing GMCH M and N values for the Display Port link |