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| author | Damien Lespiau <damien.lespiau@intel.com> | 2014-04-07 20:24:33 +0100 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2014-04-09 14:58:27 +0200 |
| commit | b76bfebab54236f90763afda9cda6cd6279b0de4 (patch) | |
| tree | 1531fc281325b900f1ffd92f72d41b825b6fdecf /drivers/gpu/drm/i915/i915_reg.h | |
| parent | 7ec55f46da2e581e0e85b17e5480dc4ae6254099 (diff) | |
| download | lwn-b76bfebab54236f90763afda9cda6cd6279b0de4.tar.gz lwn-b76bfebab54236f90763afda9cda6cd6279b0de4.zip | |
drm/i915/bdw: Provide a gen8 version of SRM
GEN8 now has a qword to code for 48bit addresses.
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_reg.h')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index c03c83c76c70..0d6202ad484d 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -267,6 +267,7 @@ */ #define MI_LOAD_REGISTER_IMM(x) MI_INSTR(0x22, 2*(x)-1) #define MI_STORE_REGISTER_MEM(x) MI_INSTR(0x24, 2*(x)-1) +#define MI_STORE_REGISTER_MEM_GEN8(x) MI_INSTR(0x24, 3*(x)-1) #define MI_SRM_LRM_GLOBAL_GTT (1<<22) #define MI_FLUSH_DW MI_INSTR(0x26, 1) /* for GEN6 */ #define MI_FLUSH_DW_STORE_INDEX (1<<21) |