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| author | Zou Nan hai <nanhai.zou@intel.com> | 2010-06-25 13:40:23 +0800 |
|---|---|---|
| committer | Eric Anholt <eric@anholt.net> | 2010-08-09 11:34:12 -0700 |
| commit | aa40d6bbb9cf88f3fb296a57e046a52e9a68ab72 (patch) | |
| tree | 1e3509cc6d080309414ff430374b5b21e1902d20 /drivers/gpu/drm/i915/i915_reg.h | |
| parent | 1cafd34731cd14e5a72edaf0f41717c8126cfce9 (diff) | |
| download | lwn-aa40d6bbb9cf88f3fb296a57e046a52e9a68ab72.tar.gz lwn-aa40d6bbb9cf88f3fb296a57e046a52e9a68ab72.zip | |
drm/i915: Set up a render context on Ironlake
RC6 power state requires a logical render context in place for saving
render context.
Signed-off-by: Zou Nan hai <nanhai.zou@intel.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_reg.h')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 21fd657663aa..a63e9a176386 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -181,6 +181,12 @@ #define MI_DISPLAY_FLIP MI_INSTR(0x14, 2) #define MI_DISPLAY_FLIP_I915 MI_INSTR(0x14, 1) #define MI_DISPLAY_FLIP_PLANE(n) ((n) << 20) +#define MI_SET_CONTEXT MI_INSTR(0x18, 0) +#define MI_MM_SPACE_GTT (1<<8) +#define MI_MM_SPACE_PHYSICAL (0<<8) +#define MI_SAVE_EXT_STATE_EN (1<<3) +#define MI_RESTORE_EXT_STATE_EN (1<<2) +#define MI_RESTORE_INHIBIT (1<<0) #define MI_STORE_DWORD_IMM MI_INSTR(0x20, 1) #define MI_MEM_VIRTUAL (1 << 22) /* 965+ only */ #define MI_STORE_DWORD_INDEX MI_INSTR(0x21, 1) @@ -1101,6 +1107,11 @@ #define PEG_BAND_GAP_DATA 0x14d68 /* + * Logical Context regs + */ +#define CCID 0x2180 +#define CCID_EN (1<<0) +/* * Overlay regs */ |