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| author | Patrik Jakobsson <patrik.jakobsson@linux.intel.com> | 2015-11-16 16:20:01 +0100 |
|---|---|---|
| committer | Imre Deak <imre.deak@intel.com> | 2015-11-17 20:55:20 +0200 |
| commit | 9f836f9016ad5320e0c9230419d2102cf15a28aa (patch) | |
| tree | 970cd25a51e98554cc7186fa9e7ea4e3edf873a5 /drivers/gpu/drm/i915/i915_reg.h | |
| parent | cd02ac52eb262f635f805d67963ad0aa0f23d6b2 (diff) | |
| download | lwn-9f836f9016ad5320e0c9230419d2102cf15a28aa.tar.gz lwn-9f836f9016ad5320e0c9230419d2102cf15a28aa.zip | |
drm/i915/gen9: Turn DC handling into a power well
Handle DC off as a power well where enabling the power well will prevent
the DMC to enter selected DC states (required around modesets and Aux
A). Disabling the power well will allow DC states again. For now the
highest DC state is DC6 for Skylake and DC5 for Broxton but will be
configurable for Skylake in a later patch.
v2: Check both DC5 and DC6 bits in power well enabled function (Ville)
v3:
- Remove unneeded DC_OFF case in skl_set_power_well() (Imre)
- Add PW2 dependency to DC_OFF (Imre)
v4: Put DC_OFF before PW2 in BXT power well array
Signed-off-by: Patrik Jakobsson <patrik.jakobsson@linux.intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
[fixed line over 80 and parenthesis alignment checkpatch warns (imre)]
Link: http://patchwork.freedesktop.org/patch/msgid/1447687201-24759-1-git-send-email-patrik.jakobsson@linux.intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/i915_reg.h')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 082408ee5789..9d879698a091 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -638,6 +638,7 @@ enum skl_disp_power_wells { /* Not actual bit groups. Used as IDs for lookup_power_well() */ SKL_DISP_PW_ALWAYS_ON, + SKL_DISP_PW_DC_OFF, }; #define SKL_POWER_WELL_STATE(pw) (1 << ((pw) * 2)) |