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| author | Damien Lespiau <damien.lespiau@intel.com> | 2015-02-09 19:33:17 +0000 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2015-02-13 23:28:34 +0100 |
| commit | 9370cd987e91d6d652ebe6d883fbc51b10df2403 (patch) | |
| tree | d72793e42e3d9ce9140d5a302f96045fa7a6c143 /drivers/gpu/drm/i915/i915_reg.h | |
| parent | 8d2054941071d10c8bbe120dd2160be8ae21f267 (diff) | |
| download | lwn-9370cd987e91d6d652ebe6d883fbc51b10df2403.tar.gz lwn-9370cd987e91d6d652ebe6d883fbc51b10df2403.zip | |
drm/i915/skl: Implement WaDisablePartialResolveInVc
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Reviewed-by: Nick Hoath <nicholas.hoath@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_reg.h')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index b00d323095af..b610764768d7 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1483,6 +1483,7 @@ enum skl_disp_power_wells { #define CACHE_MODE_1 0x7004 /* IVB+ */ #define PIXEL_SUBSPAN_COLLECT_OPT_DISABLE (1<<6) #define GEN8_4x4_STC_OPTIMIZATION_DISABLE (1<<6) +#define GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE (1<<1) #define GEN6_BLITTER_ECOSKPD 0x221d0 #define GEN6_BLITTER_LOCK_SHIFT 16 |