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| author | Paulo Zanoni <paulo.r.zanoni@intel.com> | 2012-05-04 17:18:14 -0300 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2012-05-08 13:45:33 +0200 |
| commit | 837ba00f20aa47018a3317bc7c1f058be0a92e39 (patch) | |
| tree | 1d738d6836a254c1fb7ee3ab0c502efdd20ecee7 /drivers/gpu/drm/i915/i915_reg.h | |
| parent | 5e13a0c5ec05d382b488a691dfb8af015b1dea1e (diff) | |
| download | lwn-837ba00f20aa47018a3317bc7c1f058be0a92e39.tar.gz lwn-837ba00f20aa47018a3317bc7c1f058be0a92e39.zip | |
drm/i915: DSL_LINEMASK is 12 bits only on gen2
Gen3+ is 13 bits (12:0), and on gen2 only 12 (11:0). For both the high
bits are marked reserved, read-only so continue to mask them. Bit 31
is not reserved and has a meaning.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_reg.h')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 10e71a9f8bd9..833052ef7cf5 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -2476,7 +2476,8 @@ /* Pipe A */ #define _PIPEADSL 0x70000 -#define DSL_LINEMASK 0x00000fff +#define DSL_LINEMASK_GEN2 0x00000fff +#define DSL_LINEMASK_GEN3 0x00001fff #define _PIPEACONF 0x70008 #define PIPECONF_ENABLE (1<<31) #define PIPECONF_DISABLE 0 |