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| author | Deepak M <m.deepak@intel.com> | 2015-12-04 19:47:38 +0530 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2015-12-04 17:21:36 +0100 |
| commit | 61ad992875639b0ac5866321e2edcba573f5f3a2 (patch) | |
| tree | f356787f5e4bef4af33281e2fac32f6e5871f47a /drivers/gpu/drm/i915/i915_reg.h | |
| parent | a9287dbc26569ec187b8bca0093e0ffe28abe843 (diff) | |
| download | lwn-61ad992875639b0ac5866321e2edcba573f5f3a2.tar.gz lwn-61ad992875639b0ac5866321e2edcba573f5f3a2.zip | |
drm/i915: Correct the Ref clock value for BXT
The reference clock for BXT is 19.2 MHz not 19.5 MHz, updating the
correct value here.
Signed-off-by: Deepak M <m.deepak@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Link: http://patchwork.freedesktop.org/patch/msgid/1449238659-12473-2-git-send-email-m.deepak@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/i915_reg.h')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index d326c54ff667..206b213a74e1 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -7714,7 +7714,7 @@ enum skl_disp_power_wells { #define BXT_DSI_PLL_RATIO_MAX 0x7D #define BXT_DSI_PLL_RATIO_MIN 0x22 #define BXT_DSI_PLL_RATIO_MASK 0xFF -#define BXT_REF_CLOCK_KHZ 19500 +#define BXT_REF_CLOCK_KHZ 19200 #define BXT_DSI_PLL_ENABLE _MMIO(0x46080) #define BXT_DSI_PLL_DO_ENABLE (1 << 31) |