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| author | Jesse Barnes <jbarnes@virtuousgeek.org> | 2013-10-03 11:35:46 -0700 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2013-10-04 10:17:04 +0200 |
| commit | 40e9cf649a88abea96d5756aa6f86e89cfabde6e (patch) | |
| tree | e477735291fde811d960e9d103a2eb8cd72f4f7b /drivers/gpu/drm/i915/i915_reg.h | |
| parent | a031d709bb90ce72cc016d242e8c1fef65ae9d5c (diff) | |
| download | lwn-40e9cf649a88abea96d5756aa6f86e89cfabde6e.tar.gz lwn-40e9cf649a88abea96d5756aa6f86e89cfabde6e.zip | |
drm/i915/vlv: reset DPIO on load and resume v2
DPIO needs to have common reset de-asserted on soft resets like boot and
S3. In some cases, the BIOS will have done this for us, but it should
be safe to do at runtime as well, as long as we do it when the pipes are
otherwise off.
v2: update bit name to match docs better (Ville)
reset after CRI clock select (Ville)
References: https://bugs.freedesktop.org/show_bug.cgi?id=69166
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_reg.h')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index daaabe788f21..c1017431fa5b 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -430,7 +430,7 @@ #define DPIO_MODSEL1 (1<<3) /* if ref clk b == 27 */ #define DPIO_MODSEL0 (1<<2) /* if ref clk a == 27 */ #define DPIO_SFR_BYPASS (1<<1) -#define DPIO_RESET (1<<0) +#define DPIO_CMNRST (1<<0) #define _DPIO_TX3_SWING_CTL4_A 0x690 #define _DPIO_TX3_SWING_CTL4_B 0x2a90 |