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| author | Chris Wilson <chris@chris-wilson.co.uk> | 2014-12-16 08:44:31 +0000 |
|---|---|---|
| committer | Jani Nikula <jani.nikula@intel.com> | 2014-12-16 15:04:39 +0200 |
| commit | 148b83d0815a3778c8949e6a97cb798cbaa0efb3 (patch) | |
| tree | 9158e7af035f085ed0c3e1b46f5dd1e892f5c0fe /drivers/gpu/drm/i915/i915_reg.h | |
| parent | dbea3cea69508e9d548ed4a6be13de35492e5d15 (diff) | |
| download | lwn-148b83d0815a3778c8949e6a97cb798cbaa0efb3.tar.gz lwn-148b83d0815a3778c8949e6a97cb798cbaa0efb3.zip | |
drm/i915: Invalidate media caches on gen7
In the gen7 pipe control there is an extra bit to flush the media
caches, so let's set it during cache invalidation flushes.
v2: Rename to MEDIA_STATE_CLEAR to be more inline with spec.
Cc: Simon Farnsworth <simon@farnz.org.uk>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: stable@vger.kernel.org
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_reg.h')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index eefdc238f70b..58009558cc94 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -395,6 +395,7 @@ #define PIPE_CONTROL_STORE_DATA_INDEX (1<<21) #define PIPE_CONTROL_CS_STALL (1<<20) #define PIPE_CONTROL_TLB_INVALIDATE (1<<18) +#define PIPE_CONTROL_MEDIA_STATE_CLEAR (1<<16) #define PIPE_CONTROL_QW_WRITE (1<<14) #define PIPE_CONTROL_POST_SYNC_OP_MASK (3<<14) #define PIPE_CONTROL_DEPTH_STALL (1<<13) |