diff options
| author | Gajanan Bhat <gajanan.bhat@intel.com> | 2014-08-07 01:58:24 +0530 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2014-08-08 17:43:59 +0200 |
| commit | 0948c2651413d56c90d7ee9c99d75bef82d4c351 (patch) | |
| tree | fe34563921c75641f0138f34c43ab5a122ca8038 /drivers/gpu/drm/i915/i915_reg.h | |
| parent | e2fcdaa9c951c51d558fea2cc020d89b382d702e (diff) | |
| download | lwn-0948c2651413d56c90d7ee9c99d75bef82d4c351.tar.gz lwn-0948c2651413d56c90d7ee9c99d75bef82d4c351.zip | |
drm/i915: Generalize drain latency computation
Modify drain latency computation to use it for any plane. Same function can be
used for primary, cursor and sprite planes.
v2: Adressed review comments by Imre and Ville.
- Moved clock round up in separate patch
- Added WARN check for clock and pixel size
- Simplified bit masking
- Use cursor_base instead of reg read
v3: Changed to bitwise shorthand operator for plane_dl assignment.
Signed-off-by: Gajanan Bhat <gajanan.bhat@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_reg.h')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 468ef09d698d..d0cff5630569 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -4009,6 +4009,7 @@ enum punit_power_well { #define DDL_PLANE_PRECISION_64 (1<<7) #define DDL_PLANE_PRECISION_32 (0<<7) #define DDL_PLANE_SHIFT 0 +#define DRAIN_LATENCY_MASK 0x7f /* FIFO watermark sizes etc */ #define G4X_FIFO_LINE_SIZE 64 |