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| author | Eugeni Dodonov <eugeni.dodonov@intel.com> | 2012-02-08 12:53:50 -0800 |
|---|---|---|
| committer | Jesse Barnes <jbarnes@virtuousgeek.org> | 2012-02-10 14:19:10 -0800 |
| commit | e4e0c058a19c41150d12ad2d3023b3cf09c5de67 (patch) | |
| tree | b8dbf4848dfe15d7a18fe9e75379fbd0f05dd000 /drivers/gpu/drm/i915/i915_reg.h | |
| parent | eae66b50c760233fad526edf4a0d327be17a055d (diff) | |
| download | lwn-e4e0c058a19c41150d12ad2d3023b3cf09c5de67.tar.gz lwn-e4e0c058a19c41150d12ad2d3023b3cf09c5de67.zip | |
drm/i915: gen7: Implement an L3 caching workaround.
This adds two cache-related workarounds for Ivy Bridge which can lead to
3D ring hangs and corruptions.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=41353
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=44610
Tested-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_reg.h')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 80fd6b5d4287..ca4737e5cdfd 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -3028,6 +3028,13 @@ #define DISP_TILE_SURFACE_SWIZZLING (1<<13) #define DISP_FBC_WM_DIS (1<<15) +/* GEN7 chicken */ +#define GEN7_L3CNTLREG1 0xB01C +#define GEN7_WA_FOR_GEN7_L3_CONTROL 0x3C4FFF8C + +#define GEN7_L3_CHICKEN_MODE_REGISTER 0xB030 +#define GEN7_WA_L3_CHICKEN_MODE 0x20000000 + /* PCH */ /* south display engine interrupt */ |