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| author | Eric Anholt <eric@anholt.net> | 2010-11-06 14:53:32 -0700 |
|---|---|---|
| committer | Chris Wilson <chris@chris-wilson.co.uk> | 2010-11-08 09:20:08 +0000 |
| commit | de6e2eaf2c420bb8b0d4485913ef312a5539b489 (patch) | |
| tree | b97f565029613ebe46d413038469639ee689bf99 /drivers/gpu/drm/i915/i915_reg.h | |
| parent | 629e894173c9de589913cf649deaadec4b0579bd (diff) | |
| download | lwn-de6e2eaf2c420bb8b0d4485913ef312a5539b489.tar.gz lwn-de6e2eaf2c420bb8b0d4485913ef312a5539b489.zip | |
drm/i915: Apply B-spec mandated workaround for read flushes on Ironlake.
This is not known to fix any particular bugs we have, but the spec
says to do it, and the BIOS hadn't already set it up on my system.
Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_reg.h')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index c79d4ba4fb12..09e2a5502652 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -316,6 +316,19 @@ #define ERROR_GEN6 0x040a0 +/* GM45+ chicken bits -- debug workaround bits that may be required + * for various sorts of correct behavior. The top 16 bits of each are + * the enables for writing to the corresponding low bit. + */ +#define _3D_CHICKEN 0x02084 +#define _3D_CHICKEN2 0x0208c +/* Disables pipelining of read flushes past the SF-WIZ interface. + * Required on all Ironlake steppings according to the B-Spec, but the + * particular danger of not doing so is not specified. + */ +# define _3D_CHICKEN2_WM_READ_PIPELINED (1 << 14) +#define _3D_CHICKEN3 0x02090 + #define MI_MODE 0x0209c # define VS_TIMER_DISPATCH (1 << 6) # define MI_FLUSH_ENABLE (1 << 11) |