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| author | Paulo Zanoni <paulo.r.zanoni@intel.com> | 2012-10-23 18:30:00 -0200 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2012-10-26 10:24:48 +0200 |
| commit | c9809791ae0ae3e5792fc6ad3d4a5d9658aadc62 (patch) | |
| tree | d45f5cf23c3bb15b0fa3147892a75e28b88d380a /drivers/gpu/drm/i915/i915_reg.h | |
| parent | 702e7a56af3780d8b3a717f698209bef44187bb0 (diff) | |
| download | lwn-c9809791ae0ae3e5792fc6ad3d4a5d9658aadc62.tar.gz lwn-c9809791ae0ae3e5792fc6ad3d4a5d9658aadc62.zip | |
drm/i915: convert PIPE_MSA_MISC to transcoder
Same as the other registers. This one also appeared on Haswell for the
first time, so that's why we are renaming it.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_reg.h')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 19 |
1 files changed, 10 insertions, 9 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index de3908680f37..3790503abd10 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -4556,15 +4556,16 @@ #define TRANS_CLK_SEL_DISABLED (0x0<<29) #define TRANS_CLK_SEL_PORT(x) ((x+1)<<29) -#define _PIPEA_MSA_MISC 0x60410 -#define _PIPEB_MSA_MISC 0x61410 -#define PIPE_MSA_MISC(pipe) _PIPE(pipe, _PIPEA_MSA_MISC, _PIPEB_MSA_MISC) -#define PIPE_MSA_SYNC_CLK (1<<0) -#define PIPE_MSA_6_BPC (0<<5) -#define PIPE_MSA_8_BPC (1<<5) -#define PIPE_MSA_10_BPC (2<<5) -#define PIPE_MSA_12_BPC (3<<5) -#define PIPE_MSA_16_BPC (4<<5) +#define _TRANSA_MSA_MISC 0x60410 +#define _TRANSB_MSA_MISC 0x61410 +#define TRANS_MSA_MISC(tran) _TRANSCODER(tran, _TRANSA_MSA_MISC, \ + _TRANSB_MSA_MISC) +#define TRANS_MSA_SYNC_CLK (1<<0) +#define TRANS_MSA_6_BPC (0<<5) +#define TRANS_MSA_8_BPC (1<<5) +#define TRANS_MSA_10_BPC (2<<5) +#define TRANS_MSA_12_BPC (3<<5) +#define TRANS_MSA_16_BPC (4<<5) /* LCPLL Control */ #define LCPLL_CTL 0x130040 |