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| author | Jesse Barnes <jbarnes@virtuousgeek.org> | 2011-01-04 15:09:34 -0800 |
|---|---|---|
| committer | Chris Wilson <chris@chris-wilson.co.uk> | 2011-01-19 12:36:41 +0000 |
| commit | 92f2584a083986c05fc811bbdf380c3fa7c12296 (patch) | |
| tree | b6e4f8b2e02475e455b800da05d5501d7d234e85 /drivers/gpu/drm/i915/i915_reg.h | |
| parent | 63d7bbe9ded4146e3f78e5742b119fa1fdb52665 (diff) | |
| download | lwn-92f2584a083986c05fc811bbdf380c3fa7c12296.tar.gz lwn-92f2584a083986c05fc811bbdf380c3fa7c12296.zip | |
drm/i915: add PCH DPLL enable/disable functions
With assertions to check transcoder and reference clock state.
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_reg.h')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index c739a4bbf005..53ddacc907b9 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -2899,6 +2899,7 @@ #define DREF_NONSPREAD_SOURCE_MASK (3<<9) #define DREF_SUPERSPREAD_SOURCE_DISABLE (0<<7) #define DREF_SUPERSPREAD_SOURCE_ENABLE (2<<7) +#define DREF_SUPERSPREAD_SOURCE_MASK (3<<7) #define DREF_SSC4_DOWNSPREAD (0<<6) #define DREF_SSC4_CENTERSPREAD (1<<6) #define DREF_SSC1_DISABLE (0<<1) |