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| author | Jesse Barnes <jbarnes@virtuousgeek.org> | 2013-11-15 09:32:12 -0800 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2013-11-28 11:02:06 +0100 |
| commit | 6b88f295690d3340fcbd01c1ff46991ea4f83c9f (patch) | |
| tree | d031d8a8c8b09d769cf0c596b2c1b359c3135db3 /drivers/gpu/drm/i915/i915_reg.h | |
| parent | 2f0aa30425414f3105bc29dd39bfdb40cb684393 (diff) | |
| download | lwn-6b88f295690d3340fcbd01c1ff46991ea4f83c9f.tar.gz lwn-6b88f295690d3340fcbd01c1ff46991ea4f83c9f.zip | |
drm/i915/vlv: use parallel context restore when coming out of RC6
Setting this bit restores all ring contexts in parallel rather than
serially. Matches current BWG recommendations.
Tested-by: "Meng, Mengmeng" <mengmeng.meng@intel.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Reviewed-by: Deepak S <deepak.s@inel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_reg.h')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 2658d975279b..3be449d884a7 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -4900,6 +4900,7 @@ #define GEN6_RC_CTL_RC6_ENABLE (1<<18) #define GEN6_RC_CTL_RC1e_ENABLE (1<<20) #define GEN6_RC_CTL_RC7_ENABLE (1<<22) +#define VLV_RC_CTL_CTX_RST_PARALLEL (1<<24) #define GEN7_RC_CTL_TO_MODE (1<<28) #define GEN6_RC_CTL_EI_MODE(x) ((x)<<27) #define GEN6_RC_CTL_HW_ENABLE (1<<31) |