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authorAkash Goel <akash.goel@intel.com>2015-09-18 23:39:51 +0530
committerDaniel Vetter <daniel.vetter@ffwll.ch>2015-10-07 16:06:24 +0200
commit26148bd3c0f1fbd8f2b0dae994f3195316f677db (patch)
treef08233763157645f3654cef5b0f35b45cfcb9350 /drivers/gpu/drm/i915/i915_reg.h
parent2f5945bc9076bd7b1086c1b4ac47dea8ab336e57 (diff)
downloadlwn-26148bd3c0f1fbd8f2b0dae994f3195316f677db.tar.gz
lwn-26148bd3c0f1fbd8f2b0dae994f3195316f677db.zip
drm/i915/bxt: Set time interval unit to 0.833us
Note that in Bspec you have to dig around in a section called "Timestamp bases" and Bspec update request is filed. Signed-off-by: Ankitprasad Sharma <ankitprasad.r.sharma@intel.com> Signed-off-by: Akash Goel <akash.goel@intel.com> Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com> Reviewed-by: Imre Deak <imre.deak@intel.com> [danvet: Add note about state of Bspec.] Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_reg.h')
-rw-r--r--drivers/gpu/drm/i915/i915_reg.h5
1 files changed, 4 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 07588b63d434..6be853d2233c 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2840,8 +2840,11 @@ enum skl_disp_power_wells {
#define INTERVAL_1_28_US(us) (((us) * 100) >> 7)
#define INTERVAL_1_33_US(us) (((us) * 3) >> 2)
+#define INTERVAL_0_833_US(us) (((us) * 6) / 5)
#define GT_INTERVAL_FROM_US(dev_priv, us) (IS_GEN9(dev_priv) ? \
- INTERVAL_1_33_US(us) : \
+ (IS_BROXTON(dev_priv) ? \
+ INTERVAL_0_833_US(us) : \
+ INTERVAL_1_33_US(us)) : \
INTERVAL_1_28_US(us))
/*