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| author | Ben Widawsky <ben@bwidawsk.net> | 2012-11-04 09:21:30 -0800 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2012-11-11 23:51:44 +0100 |
| commit | 0f9b91c754b7244d3a7345df88c4384f0eb0dd17 (patch) | |
| tree | 3a4feddfd1b3f1e8bce1fcb095dc1d243d839e82 /drivers/gpu/drm/i915/i915_reg.h | |
| parent | 009946f89b7795699848a922fc2f7804390017d9 (diff) | |
| download | lwn-0f9b91c754b7244d3a7345df88c4384f0eb0dd17.tar.gz lwn-0f9b91c754b7244d3a7345df88c4384f0eb0dd17.zip | |
drm/i915: flush system agent TLBs on SNB
This allows us to map the PTEs WC. I've not done thorough testing or
performance measurements with this patch, but it should be decent.
This is based on a patch from Jesse with the original commit message
> I've only lightly tested this so far, but the corruption seems to be
> gone if I write the GFX_FLSH_CNTL reg after binding an object. This
> register should control the TLB for the system agent, which is what CPU
> mapped objects will go through.
It has been updated for the new AGP-less code by me, and included with
it is feedback from the original patch.
v2: Updated to reflect paranoia on pte updates/register posting reads.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by [v1]: Jesse Barnes <jbarnes@virtuousgeek.org>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_reg.h')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index e62b347dc049..d55c49642c68 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -694,6 +694,8 @@ #define CM0_RC_OP_FLUSH_DISABLE (1<<0) #define BB_ADDR 0x02140 /* 8 bytes */ #define GFX_FLSH_CNTL 0x02170 /* 915+ only */ +#define GFX_FLSH_CNTL_GEN6 0x101008 +#define GFX_FLSH_CNTL_EN (1<<0) #define ECOSKPD 0x021d0 #define ECO_GATING_CX_ONLY (1<<3) #define ECO_FLIP_DONE (1<<0) |