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| author | Daniel Vetter <daniel.vetter@ffwll.ch> | 2012-07-05 12:17:29 +0200 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2012-07-05 13:34:14 +0200 |
| commit | e506a0c6381f180858d2e343c3ed5c0bde8e84ba (patch) | |
| tree | c5a531a2d62bcb1f2ecd0b6913677af78d91edf7 /drivers/gpu/drm/i915/i915_reg.h | |
| parent | e6a595d2db7ad403fcb2b7b168754d7551fc8c9b (diff) | |
| download | lwn-e506a0c6381f180858d2e343c3ed5c0bde8e84ba.tar.gz lwn-e506a0c6381f180858d2e343c3ed5c0bde8e84ba.zip | |
drm/i915: introduce crtc->dspaddr_offset
To avoid recomputing the display framebuffer offset on gen2/3
pageflips. This is also prep work to do similar trickery on gen4+
Also:
- kill "Start", such upper-case remnants from the ddx must surely die.
- rename "Offset" to linear_offset, to make it clearer that on gen4+
this is only used by the hw for linear buffers, for tiled buffers it
uses the TILEOFF register.
- call DSAPADDR DSPLINOFF on gen4+ for the same reason (and because
the documentation really renamed the register).
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-Off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_reg.h')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 1bd17e7dd479..4a2ea42b5ecf 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -2979,6 +2979,7 @@ #define DSPSIZE(plane) _PIPE(plane, _DSPASIZE, _DSPBSIZE) #define DSPSURF(plane) _PIPE(plane, _DSPASURF, _DSPBSURF) #define DSPTILEOFF(plane) _PIPE(plane, _DSPATILEOFF, _DSPBTILEOFF) +#define DSPLINOFF(plane) DSPADDR(plane) /* Display/Sprite base address macros */ #define DISP_BASEADDR_MASK (0xfffff000) |