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| author | Mika Kuoppala <mika.kuoppala@linux.intel.com> | 2015-03-24 14:54:19 +0200 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2015-03-25 18:23:44 +0100 |
| commit | 6c826f349587f6c897da9bd224912ca1aee3d9ea (patch) | |
| tree | a6945a1ee5c4f9f98e0c22aae3f20de1fce5f968 /drivers/gpu/drm/i915/i915_reg.h | |
| parent | 1d00dad56b15ed5dab5802143df2bf61d51b6b55 (diff) | |
| download | lwn-6c826f349587f6c897da9bd224912ca1aee3d9ea.tar.gz lwn-6c826f349587f6c897da9bd224912ca1aee3d9ea.zip | |
drm/i915: Add fault address to error state for gen8 and gen9
The faulting virtual address is >32bits and has been moved
to different registers. Add to error state and output upper
register first, in the same line for easy reconstruction of
the fault address.
v2: correct gen masking (Michel)
v3: s/TBL/TLB (Ville)
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
Reviewed-by: Michel Thierry <michel.thierry@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_reg.h')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 5b84ee686f99..b522eb6e59a4 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1306,6 +1306,9 @@ enum skl_disp_power_wells { #define ERR_INT_FIFO_UNDERRUN_A (1<<0) #define ERR_INT_FIFO_UNDERRUN(pipe) (1<<(pipe*3)) +#define GEN8_FAULT_TLB_DATA0 0x04b10 +#define GEN8_FAULT_TLB_DATA1 0x04b14 + #define FPGA_DBG 0x42300 #define FPGA_DBG_RM_NOCLAIM (1<<31) |