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| author | Deepak S <deepak.s@linux.intel.com> | 2014-05-15 20:58:09 +0300 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2014-05-15 23:14:56 +0200 |
| commit | baccd4586ed948569207de83f28772376d5c3772 (patch) | |
| tree | ff9e5de0ec804818ca54280f55b59c5ebbc9b4ba /drivers/gpu/drm/i915/i915_reg.h | |
| parent | 0961021aef788e9d0d4e34256655d6c761ef716b (diff) | |
| download | lwn-baccd4586ed948569207de83f28772376d5c3772.tar.gz lwn-baccd4586ed948569207de83f28772376d5c3772.zip | |
drm/i915: Enable PM Interrupts target via Display Interface.
In BDW, Apart from unmasking up/down threshold interrupts. we need
to umask bit 32 of PM_INTRMASK to route interrupts to target via Display
Interface.
v2: Add (1<<31) mask (Ville)
v3: Add Gen check for the mask (ville)
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Deepak S <deepak.s@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_reg.h')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 76fdfc2fb835..ac90786dbb25 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -5311,6 +5311,7 @@ enum punit_power_well { #define VLV_RCEDATA 0xA0BC #define GEN6_RC6pp_THRESHOLD 0xA0C0 #define GEN6_PMINTRMSK 0xA168 +#define GEN8_PMINTR_REDIRECT_TO_NON_DISP (1<<31) #define VLV_PWRDWNUPCTL 0xA294 #define GEN6_PMISR 0x44020 |